1. Field of the Invention
The present invention relates generally to electrical circuits having cascade features utilizing normally-off junction field effect transistors having low on-resistance for low voltage and high current density applications. More particularly, these electrical circuits are configured to provide amplification of an input signal and signal switching capabilities.
2. Description of the Prior Art
Increasing attention within the semiconductor industry focuses on providing low voltage and low power circuitry capable of handling high current densities for use in a wide range of power sensitive applications such as cellular and cordless telephones, laptop personal computers, and personal digital assistants.
More specifically, circuits having cascade features, whereby two similarly configured circuit elements are coupled together, have been designed using the conventionally designed junction field effect transistor (JFET). However, the conventional JFET has seen,limited use primarily because of its normally-on state when the gate bias is zero and also because of its typically high on-resistance. Additionally, conventional JFET applications are unsuitable for operating at the lower voltages, higher current densities, and lower on state voltage drops necessitated by power sensitive applications.
In general, the junction field effect transistor is desirable in electrical circuits because it can be operated at very high frequencies and high switching speeds since it uses majority carriers. Prior Art FIGS. 1A, 1B, 1C, and 1D show conventional configuration and operational characteristics of a JFET. The JFET operates as a voltage-controlled device in which the voltage at the gate controls the amount of current through the device. A conventional JFET is normally in an on-state, e.g. a freely conducting state. The JFET is turned off by reverse-biasing the voltage between the gate and source. As such, a depletion region of high resistance expands through the conduction channel between the source and drain thereby reducing the cross-sectional area of the conduction channel and effectively shutting off the JFET. For an n-channel JFET as shown in Prior Art FIG. 1B, a negative voltage applied to the gate will pinch off the conduction channel. Conversely, in a p-channel transistor, a positive voltage applied to the gate will pinch off the conduction channel.
Therefore, it would be desirable to provide electrical circuits with cascade features of varying capabilities which are capable of operating under low voltage, low on-resistance, and high current density situations. In particular, it would be desirable to provide for signal amplification. It would also be desirable to provide for circuit switching capabilities for controlling motors, switching power supplies, and other applications.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.
In the present invention, a cascade circuit using normally-off junction field effect transistors (JFETs) is configured to amplify an input signal and capable of operating under low on-resistance, low voltages, and high current densities. The present invention also discloses a cascade circuit using normally-off JFETs configured to have switching characteristics and capable of operating under low on-resistance, low voltages and high current densities in a normally-off state.
Specifically, embodiments of the present invention comprise a three terminal gate-controlled cascade amplification circuit capable of signal amplification formed by two or more properly coupled normally-off junction field effect transistors supported on a substrate. In one embodiment, two normally-off JFETs are used for signal amplification where the source electrode from the first JFET is coupled to the gate electrode of the second JFET. Accordingly, three terminal control of the cascade amplification circuit is provided by the gate of the first JFET, coupling the drain electrodes from both JFETs, and lastly the source of the second JFET.
In another embodiment of the present invention, a four terminal gate-controlled cascade switching circuit is formed by properly coupling two normally-off JFETs supported on a substrate. The cascade switching circuit switches on to allow current to flow between the source and drain electrodes of the second JFET. The cascade switching circuit switches off to impede current flow between the source and drain electrodes of the second JFET. For four terminal operation, the source electrode from the first JFET is coupled to the gate electrode of the second JFET. Accordingly four terminal control of the cascade switching circuit is provided by the gate and drain electrodes of the first JFET, and the source and drain electrodes of the second JFET.